In many multiple-processor computer systems it is important for processes or tasks running on one computer node (sometimes called the sender) to be able to transmit a message or data to another computer node (sometimes called the receiver). Generally, transmitting messages between computer nodes is expensive in terms of latency and resources used if the successful transmission of each message is verified by performing a remote read operation after each such remote message write operation.
Alternately, instead of using remote reads to verify the successful transmission of each message, in some prior art systems a message is written locally to a local buffer, and then a "cookie" (which is primarily a data structure pointing to the memory location or locations where the message is stored) or other notification message is sent to the receiving system. The receiving system then performs a remote read operation to read the message from the remote memory location indicated in the notification message. In another implementation of this same basic prior art technique, both the message and the cookie are stored locally in the sending system and only a trigger message is transmitted to the receiving system. The receiving system responds to the trigger message by performing a first remote read operation to read the cookie and a second remote read operation to read the message at the location indicated by the cookie.
An advantage of the prior art techniques using remote read operations as an integral part of every message transmission is that remote reads are synchronous, and thus the system performing the remote read is notified immediately if the message transmission fails.
Another advantage of using remote read operations to transmit messages is that remote read operations make it relatively easy to ensure that each message is received and processed by the receiving system once and only once. In most networked computer systems it is essential not to send the receiving system the same message twice. Sending the same message twice could cause the receiving system to perform an operation twice that should only be performed once. Each message must be reliably received and processed by the receiving system exactly once to ensure proper system operation.
Remote write operations are relatively "inexpensive," compared to remote read operations, in terms of system latency and system resources used, because a remote write can be "performed and forgotten."
Referring to FIG. 1, there is shown a highly simplified representation of two prior art computer nodes herein called Node A 50, and Node B 52. The computer at each node can be any type of computer. In other words, the particular brand, architecture and operating system is of no importance to the present discussion, so long as each computer node is configured to operate in a networked environment. Each computer node 50, 52 will typically include a central processing unit (CPU) 54, random access memory 56, an internal memory bus 58 and a communications interface 60, often called a network interface card (NIC). The computer nodes communicate with each other by transmitting messages or packets to each other via a network interconnect 62, which may include one or more types of communication media, switching mechanisms and the like.
Each computer node 50, 52 typically also has a non-volatile, non-random access memory device 64, such as a high speed magnetic disk, and a corresponding disk controller 66.
FIG. 2 shows a simplified representation of a conventional communications interface (or NIC) 60, such the ones used in the computer nodes of FIG. 1, showing only the components of particular interest. The NIC 60 typically includes two address mapping mechanisms: an incoming memory management unit (IMMU) 70 and an outgoing memory management unit (OMMU) 72. The purpose of the two memory management units are to map local physical addresses (PA's) in each computer node to global addresses (GA's) and back. Transport logic 74 in the NIC 60 handles the mechanics of transmitting and receiving message packets, including looking up and converting addresses using the IMMU 70 and OMMU 72.
The dashed lines between the memory bus 60 and the IMMU 70 and OMMU 72 represent CPU derived control signals for storing and deleting address translation entries in the two MMU's, typically under the control of a NIC driver program. The dashed line between the memory bus 60 and the transport logic 74 represents CPU derived control signals for configuring and controlling the transport logic 74.